In the layout and fabrication of bipolar integrated circuits, a thin silicon epitaxial layer formed on a silicon substrate is subdivided into electrically isolated islands by a grid of oxidized regions of epitaxial silicon referred to as oxidized isolation regions, isolation oxide regions, or field oxide regions. The now classic method of oxide isolation of epitaxial islands is described by Douglas L. Peltzer in U.S. Pat. No. 3,648,125. The annular shaped isolation oxide regions defining and separating the epitaxial islands extend through the epitaxial layer to the laterally extending PN Junction between the epitaxial layer and substrate.
Active and passive integrated circuit structures or circuit elements such as transistors, diodes, and resistors are then formed in the epitaxial islands by a sequence of masking and implanting steps selectively introducing P type and N type dopant materials into different regions of the epitaxial islands. Typically, a buried layer composed of N+ silicon semiconductor material is formed in a P type substrate below the epitaxial island, underlying the circuit elements of the epitaxial island. The plus sign "+" indicates the higher density or higher concentration implant of buried layer N type impurity resulting in greater conductivity. The buried layers provide buried collector layers for transistors and are joined to the transistor collector taps by collector sink regions, for example as described in the Paul J. Howell, et al. U.S. Pat. No. 4,498,227. Channel stop regions, for example of P+ concentration silicon or semiconductor material, are formed below the isolation oxide between epitaxial islands and between buried collector layers to avoid or reduce parasitic metal oxide silicon (MOS) field effect transistor (FET) effects between epitaxial islands. Such use of channel stop regions is further described for example in the Donald J. Desbiens et al. U.S. Pat. Application Ser. No. 940,573 filed Dec. 11, 1986 entitled "Enhanced Density Modified Isoplanar Process."
A disadvantage of the conventional layout of integrated circuit elements with buried collector layers and channel stop regions is the problem of feed through of AC signals between circuit elements. NPN transistor elements of the epitaxial islands are capacitively coupled to the substrate through the buried collector layers. Channel stop regions provide low resistance paths through the substrate between the capacitively coupled transistor buried layer regions. Because of the integrated circuit package lead inductance and inductive impedance, there is insufficient return of AC signal noise through the substrate taps and leads, and high frequency substrate currents can follow the relatively low resistance channel stop path between circuit elements as an alternate return path. The problem is increased in digital to analog converters (DAC's) containing high speed switching digital circuits as well as wideband analog circuits on the same substrate. High frequency switching noise from the digital transistors is capacitively coupled from the buried collector layers to the relatively low resistance channel stop region substrate paths and is superimposed on sensitive analog circuit nodes.
A conventional approach to reduceing feed through coupling of high frequency switching noise is to provide abundant spacing between the NPN buried collector layers and the channel stop regions. The increased spacing and higher resistance of intermediate substrate material reduces the capacitive feed through coupling or loading but at the expense of increased and excessive layout size. Integrated component spacing and integrated circuit size cannot be minimized thereby losing the benefits of the minimum spacing otherwise permitted by oxide isolation of the epitaxial islands.
Another conventional method of reducing or eliminating high frequency AC signal noise is to filter out the switching noise using filters incorporated in the analog circuits. Flipflop digital circuits may have switching frequencies for example in the range of hundreds f megahertz, and risetimes less than 300pS. In the case of a wideband output analog circuit, the switching speed noise may be within the bandwidth of the wideband analog circuit output. The bandwidth must be preserved and such filtering is therefore inapplicable or inappropriate.